1. Field of the Invention
The present invention is directed to a method of processing a semiconductor device having topographical features therein. More specifically, the process of the present invention is directed to providing means for electrical interconnection capability to a semiconductor device without introducing debris into topographical features resulting from such processing.
2. Background of the Prior Art
The continuing decrease in size of semiconductor devices, which include semiconductor wafers, semiconductor chips, ceramic substrates, patterned film structures and the like, have resulted in increased failure rates due to shorts and other defects in the electrical pattern disposed upon the semiconductor device.
As indicated above, it is the ever increasing miniaturization of semiconductor devices that has created these problems. Specifically, a major cause of increased electrical failures has been the inability to remove debris from topographical features due to the inability of traditional solvents from penetrating therein to remove debris that disturbs the resulting electrical conductivity on and between semiconductor devices.
The preparation of electrical interconnection of a semiconductor device requires that an electrically conductive layer be disposed in topographical features of the semiconductor device so that electrical conductivity paths can be later introduced thereon. However, as those skilled in the art are aware, the electrically conductive layer must be removed from those portions of the semiconductor device, principally the surface, where no electrical conductivity is desired. This is accomplished by chemical mechanical polishing. However, this polishing step oftentimes results in the deposition of debris into the typographical surfaces. Indeed, a discussion of this problem is set forth in U.S. Pat. No. 6,126,853.
In the prior art, the removal of unwanted conductive material after formation of seed layers and other such materials by chemical mechanical processing, which resulted in the deposition of debris into topographical features, was accomplished by utilizing wet chemical cleaning processes of the type set forth in U.S. Pat. No. 5,972,124. Unfortunately, as semiconductor devices have become smaller and smaller, even reaching the nanometer size, the ability of conventional cleaning solvents to penetrate into such topographical features has markedly diminished. As such, prior art processes are incapable of providing satisfactory processing of the most recently developed semiconductor devices to provide those devices with electrical interconnection capability. There is therefore a strong need in the art for a new process of providing electrical interconnection of semiconductor devices.
A new process has now been developed which permits electrical interconnection of semiconductor devices even when the semiconductor devices themselves are of such small size and possessed of such high aspect ratios that conventional cleaning materials cannot penetrate into topographical features thereon.
In accordance with the present invention a process of providing a semiconductor device, having topographical features with electrical interconnection capability, is provided. In this process an electrically conductive seed layer is deposited thereon. This is followed by the deposition of a layer of a sacrificial material which is soluble in liquid or supercritical carbon dioxide. The semiconductor device is thereupon polished with a chemical mechanical polish to remove the unwanted seed layer material and the sacrificial material from all but the topographical features of the semiconductor device. The sacrificial material is then removed from the topographical features of the semiconductor device by contacting the device with liquid or supercritical carbon dioxide.